1. Field of the Invention
The present invention relates to a technique of designing a semiconductor device. In particular, the present invention relates to a technique of designing a semiconductor device based on a clock tree synthesis method.
This application is based upon and claims the benefit of priority from Japanese patent application No. 2007-054377, filed on Mar. 5, 2007, the disclosure of which is incorporated herein in its entirely by reference.
2. Description of Related Art
In designing a semiconductor device, placement of macro cells and basic cells is performed, and then routing between the cells is performed. The basic cells (primitive cells) include a logic gate cell such as a NAND and an inverter, a clock source cell for supplying a clock, a flip-flop cell that operates based on the clock, and the like.
In a clock design process, it is desirable to reduce clock skew between a plurality of flip-flop cells which are placed in the cell placement process. A method for that purpose is the CTS (Clock Tree Synthesis). According to the CTS, clock driver cells (clock buffer cells) are properly placed such that uniform interconnection lengths from a clock source cell to respective flip-flop cells and uniform clock drive capabilities for the respective flip-flop cells are achieved. Consequently, the clock skew between the flip-flop cells is reduced.
Japanese Laid-Open Patent Application JP-A-Heisei, 11-3942 discloses a layout placement method of a semiconductor device. According to the method, a placement prohibited region is defined around each of the clock source cell, the clock buffer cell and the flip-flop cell. In the cell placement process, each of the clock source cell, the clock buffer cell and the flip-flop cell is treated as having a pseudo size equivalent to the placement prohibited region, and such cells each having the pseudo size equivalent to the placement prohibited region are first placed. Next, logic cells whose power consumption is relatively high are placed. After that, the above-mentioned cells each having the pseudo size are replaced with original cells, respectively. Subsequently, logic cells whose power consumption is relatively low are placed. Consequently, the cells synchronized with a clock signal and the high power consumption cells are prevented from being placed adjacent to each other.
The inventors of the present application have recognized the following point. One of highest consumption current basic cells in a semiconductor chip is the clock driver cell. If the clock driver cells are densely placed, a local current concentration possibly occurs in a power line. The local current concentration causes disconnection due to electromigration and property fluctuation (increase in interconnect resistance) due to Joule heating.